the first counter's clk pulse have an frequency of 1Hz sothe time will be 1sec(duty cycle must de 50), the other counters clk pulse is output of the first counter. using a logic ckt when the four inputs are zero the second clk pulse is given. by that when the counter 1 read the digit 0 the counter 2 reads 1 and go on.
components required:
IC 7476,7400,7432,7447 & 7 segment display
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